Field effect transistor structure having notched mesa

ABSTRACT

A Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a Divisional application of application Ser. No. 14/707,435, filed May 8, 2015, which application is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

This disclosure relates generally to Field Effect Transistor (FET) Structures and more particularly to FET structures having reduced gate parasitics.

BACKGROUND

As is known in the art, as the frequency of FET (Field Effect Transistor) operation goes above 90 GHz toward THz range, both gate and channel lengths of FETs are reduced to sub-80 nm range towards 20 nm according to recent publications. At these small geometries, parasitic resistance, inductance, and capacitance of the FETs significantly affect the RF performance of the FET device, such as power, gain and efficiency. Most of attempts to increase the operating frequency of FET have focused on using smaller gate length and width, and narrow channel.

More particularly, a FET according to the PRIOR ART is shown in FIGS. 1A-1C. Here, a semi-insulating, highly resistive, substrate, such as SiC, has formed on the upper surface thereof a mesa shaped semiconductor structure, here for example a Group III-V structure, here, for example, a GaN structure. More particularly, III-V based structures such as GaN-based transistors use electrons formed between two different bandgap materials, for example, AlGaN and GaN. Formed in ohmic contact with source and drain regions of the upper surface of the mesa are source and drain electrodes, as shown. Disposed between the source and drain electrodes is a gate electrode in Schottky contact with an upper surface of the mesa (a gate region) disposed between the source and drain regions. The gate electrode is used to control a flow of carriers (holes and electrons) in an active region of the mesa though the active region (sometimes herein referred to as the gate channel region) between the source and drain regions. It is noted that the regions outside of the mesa area, called ‘off mesa area’. The off mesa area, as noted above, is semi-insulating highly resistive area. The Effective gate width (the active region) is the length of the gate electrode is the region closest to the source and drain regions (the gate channel region) and it is this gate channel region that contributes to the conduction of transistor. As the gate channel width (the distance between the source and drain) gets narrower to reduce the electron transfer time for high frequency operation, the contribution of the carriers in the gate channel region gets stronger. From the prior art it is noted that the total gate length extends beyond the gate channel length even though the most of carrier conduction occurs along the gate channel length; however, the portions of the gate electrode extending beyond the gate channel region generate parasitic gate resistance, inductance, and capacitance and thereby contribute negatively for high frequency operation.

Next, it is noted that the source electrode is disposed within opposing sidewalls of the mesa structure, the drain electrode is disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa, and the gate electrode is disposed within opposing walls of the gate region of the mesa and that the mesa is rectangular shape. Further, it is noted that the source electrode has an inner edge extending between ends SOURCE EDGE 1, SOURCE EDGE 2 (FIG. 1A) thereof proximate the gate electrode that extends along a direction parallel to the gate electrode; and, likewise the drain electrode has an inner edge extending between ends DRAIN EDGE 1, DRAIN EDGE 2 (FIG. 1A) thereof proximate the gate electrode that extends along a direction parallel to the gate electrode. The lengths of the inner edges of the source and drain electrodes are equal. The gate electrode extends beyond the ends of SOURCE EDGE 1, SOURCE EDGE 2 of the inner edge of the source electrode and thus also beyond the ends of DRAIN EDGE 1, DRAIN EDGE 2 of the inner edge of the drain electrode. The active region (gate channel) extends between ends DRAIN EDGE 1 (or SOURCE EDGE 1) and DRAIN EDGE 2 (or SOURCE EDGE 2) (FIG. 1A). As noted above, the total gate electrode length extends beyond the active region (gate channel length), even though the most of carrier conduction occurs along the gate channel length, generates unwanted parasitic gate resistance, inductance, and capacitance and thereby contributes negatively for high frequency operation of the FET.

SUMMARY

In accordance with the present disclosure, a Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa structure; and a gate electrode, having an inner portion disposed between, and laterally of the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure.

In one embodiment, the mesa structure includes a pair of notches project inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.

With such an arrangement, the gate parasitics of the prior art are reduced by the formation of the notches in the mesa structure because extra gate length on top of the active region of the mesa structure is eliminated and the gate tab (or pad) disposed on the substrate off of the mesa structure is able to be positioned closer to active inner portion of the gate. With a multi-fingered gate structure, as the number of gate fingers increases, the parasitic components are multiplied and therefore the disclosed FET structure significantly improves the performance of FETs with multiple gate fingers at high operating frequency.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

FIGS. 1A-1C are plan, and cross sectional views of a Field Effect Transistor structure according to the PRIOR ART, where the cross sectional views in FIGS. 1B and 1C are taken along lines 1B-1B and 1C-1C, respectively, in FIG. 1A;

FIGS. 2A-2C are plan, and cross sectional views of a Field Effect Transistor structure according to the disclosure, where the cross sectional views in FIGS. 2B and 2C are taken along lines 2B-2B and 2C-2C, respectively, in FIG. 2A;

FIG. 3 is a plan view of the Field Effect Transistor structure of FIG. 1A disposed in a side-by-side relationship with the Field Effect Transistor structure of FIG. 2B to compare the two Field Effect Transistor structures; and

FIG. 4 is a plan view of a multi-gate embodiment of a Field Effect Transistor structure according to the disclosure.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Referring now to FIGS. 2A-2C, a Field Effect Transistor structure 10 is shown having: a semi-insulating substrate 12, here for example, a semi-insulating, highly resistive, substrate, such as SiC, GaAs, and InP; a semiconductor mesa structure 14, here for example, a Group III-V structure such as a GaN structure, disposed on the upper surface 16 of the substrate 12 and having a pair of notches 18 in opposing outer sidewalls 20 of the mesa structure 14; a source electrode 22 disposed within the opposing sidewalls 20 in ohmic contact with a source region 24 (FIG. 2C) of the mesa structure 14 under the source electrode 22; a drain electrode 26 disposed within the opposing sidewalls 20 in ohmic contact with a drain region (not shown) under the drain electrode 26 of the mesa structure 14; and a gate electrode 28, having an inner portion 28 a disposed between, and laterally of the source electrode 22 and the drain electrode 26 and in Schottky contact with the portion of the mesa structure 14 under the inner portion of the gate electrode 28 a, extending longitudinally between the pair of notches 18 and having outer portions 28 b extending beyond the mesa structure 14 and over portions of the upper surface 16 of substrate 12 outside of the mesa structure 14 (“off-mesa”). Thus, here the mesa structure 14 includes a pair of notches 18 which project inwardly towards each other and the inner portion 28 a of the gate 28 extends longitudinally between the pair of notches 18. It is noted that here the notches 18 are v-shaped notches. It should be understood, however, that the notches 18 may be of a different shapes and includes, for example, any shaped indentation or groove in the sidewalls 20 of the mesa structure 14, including, for example, a rounded indentation, a square or rectangular indentation.

Further, it is noted that the source electrode 22 has an inner edge 23 extending between ends SE 1 and SE2 (FIG. 2A) thereof proximate the inner portion 28 a of gate electrode 28; and, likewise the drain electrode 26 has an inner edge 27 extending between ends DE1, DE2 (FIG. 2A) thereof proximate the inner portion 28 a of gate electrode 28. Here, the lengths of the inner edges 23, 27 of the source and drain electrodes 22, 26 are equal. The gate electrode 28 extends beyond the ends SE1, SE2 of the inner edge 23 of the source electrode 22 and thus also beyond the ends DE1, DE2 of the inner edge 27 of the drain electrode 26. The active region (gate channel) 29 in under the inner portion 28 a of the gate electrode 28 and extends between ends DE1 (or SE1) and DE2 (or SE2) (FIG. 2A).

It is noted that the inner portion 28 a of the gate electrode 28 is elongated and the source electrode 22 and the drain electrode 26 are here also elongated along directions parallel to the direction of the elongated inner portion 28 a of the gate electrode 28. It is also noted that the source electrode 22 is within opposing outer portions of the sidewalls 20 of the mesa structure 14 separated a length L_(ms) measured along the top surface of the mesa; the drain electrode is within opposing portions of the sidewalls 20 separated a length L_(md) measured along the top surface of the mesa; and the inner portion 28 a of the gate electrode 28 is within the pair of notches 18, the notches being separated a length L s measured along the top surface of the mesa; where L_(mg) is less than either one of the lengths L_(md) or L_(ms); it here being noted that length L_(md) equals length L_(ms). It is noted that all three lengths are measured along directions parallel to the direction of the elongated inner portion 28 a of the gate electrode 28. One end of the inner portion 28 a of the gate electrode 28 terminates in a gate pad 28 p and a portion 28 p′ of the gate pad 28 p is disposed within a portion of one of the pair of notches 18, here the notch 28 on the right hand side of mesa structure 14 in FIG. 2A. The gate pad 28 p is wider than the inner region 28 a of the gate electrode 28.

Referring now to FIG. 3, a comparison is shown between the plan view of a mesa structure with a pair of opposing notches (the upper portion of FIG. 3) and a mesa structure without a pair of opposing notches (the lower portion of FIG. 3). It is noted that the length of the gate electrode between the end of the active gate region and the gate pad on the right hand side of FIG. 3 with the notch is less than the length of the gate electrode between the end of the active gate region and the gate pad without the notch by a difference in length DIFF1. Similarly, it is noted that the length of the gate electrode between the end of the active gate region and the left hand end of the gate electrode with the notch is less than the length of the gate electrode between the end of the active gate region and the left hand end of the gate electrode without the notch by a difference in length DIFF2. Thus, the gate parasitics are reduced by the formation of the notches in the mesa structure because extra gate length on top of the active region of the mesa structure is eliminated and the gate tab (or pad) disposed on the substrate off of the mesa structure is able to be positioned closer to active inner portion of the gate.

Referring now to FIG. 4, a multi-fingered gate structure, here having two gate fingers, it being understood that more than two gate fingers may be used, of the FET of FIGS. 2A-2C is shown. Here, the source electrode is connected to a ground plane on the bottom surface of the substrate with a conductive via passing vertically through the mesa structure and the underlying portion of the substrate. It is noted that as the number of gate fingers increases, the parasitic components are multiplied and therefore the disclosed FET structure significantly improves the performance of FETs with multiple gate fingers.

A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims. 

What is claimed is:
 1. A Field Effect Transistor, comprising: a structure having a substrate with a Group III-V semiconductor mesa, the Group III-V semiconductor mesa having a notch projecting both horizontally into a side of the Group III-V semiconductor mesa and vertically into an upper surface of the Group III-V semiconductor mesa, the notch being disposed over portions of the substrate outside of the Group III-V semiconductor mesa; and a source electrode in ohmic contact with the Group III-V semiconductor mesa; a drain electrode in ohmic contact with the Group III-V semiconductor mesa; a gate electrode having: a first portion disposed on the Group III-V semiconductor mesa for controlling a flow of carriers between the source electrode and the drain electrode through the Group III-V semiconductor mesa; and a second portion extending longitudinally from, and connected to, the first portion, the second portion comprising a gate pad being both: wider than the first portion; and disposed over the portions of the substrate outside of the Group III-V semiconductor mesa and under the notch; and wherein the gate pad has a first portion disposed within the notch and a second portion, wider than the first portion, disposed outside the notch.
 2. The Field Effect Transistor structure recited in claim 1 wherein the Group III-V semiconductor mesa includes a pair of notches projecting inwardly towards each other and wherein the inner portion of the gate extends longitudinally between the pair of notches.
 3. The Field Effect Transistor structure recited in claim 1 wherein: the source electrode is within opposing outer edges separated a length L_(ms) measured along the upper surface of the Group III-V semiconductor mesa; the drain electrode is within opposing outer edges separated a length L_(md) measured along the upper surface of the Group III-V semiconductor mesa; the first portion of the gate is within the notch and an opposing edge having a separation a length L_(mg) measured along the upper surface of the Group III-V semiconductor mesa; where L_(mg) is less than either on of L_(md) or L_(ms).
 4. The Field Effect Transistor structure recited in claim 2 wherein: the source electrode is within opposing outer edges the Group III-V semiconductor mesa separated a length L_(ms); the drain electrode is within opposing outer edges the Group III-V semiconductor mesa separated a length L_(md); the first portion of the gate is within the pair of notches having a separation a length L_(mg); where L_(mg) is less than either on of L_(md) or L_(ms).
 5. The Field Effect Transistor structure recited in claim 1 wherein the Group III-V semiconductor mesa comprises a mesa structure.
 6. The Field Effect Transistor structure recited in claim 3 wherein the Group III-V semiconductor mesa comprises a mesa structure.
 7. The Field Effect Transistor recited in claim 1 wherein the gate electrode is spaced from the source region and the drain region.
 8. The Field Effect Transistor recited in claim 1 wherein a carrier control portion of the first portion of the gate electrode controls the flow of carriers between the source electrode and the drain electrode through an active region closest to the source electrode and the drain electrode; wherein the notch is separated from the active region closest to the source electrode and the drain electrode by a portion of the Group III-V semiconductor mesa; and wherein the carrier control portion of the first portion of the gate electrode is in Schottky contact with only the upper surface of the Group III-V semiconductor mesa.
 9. A Field Effect Transistor, comprising: a structure having a substrate with a Group III-V semiconductor region, the Group III-V semiconductor region having a notch projecting both horizontally into a side of the Group III-V semiconductor region and vertically into an upper surface of the Group III-V semiconductor region, the notch being disposed over portions of the substrate outside of the Group III-V semiconductor region; and a source electrode in ohmic contact with the Group III-V semiconductor region; a drain electrode in ohmic contact with the Group III-V semiconductor region; a gate electrode having: a first portion disposed on the Group III-V semiconductor region for controlling a flow of carriers between the source electrode and the drain electrode through the Group III-V semiconductor region; and a second portion extending longitudinally from, and connected to, the first portion, the second portion comprising a gate pad being both: wider than the first portion; and disposed over the portions of the substrate outside of the Group III-V semiconductor region and under the notch; and wherein the gate pad has a first portion disposed within the notch and a second portion, wider than the first portion, disposed outside the notch.
 10. The Field Effect Transistor structure recited in claim 9 wherein the Group III-V semiconductor region includes a pair of notches projecting inwardly towards each other and wherein the inner portion of the gate extends longitudinally between the pair of notches.
 11. The Field Effect Transistor structure recited in claim 9 wherein: the source electrode is within opposing outer edges separated a length L_(ms) measured along the upper surface of the Group III-V semiconductor region; the drain electrode is within opposing outer edges separated a length L_(md) measured along the upper surface of the Group III-V semiconductor region; the first portion of the gate is within the notch and an opposing edge having a separation a length L_(mg) measured along the upper surface of the Group III-V semiconductor region; where L_(mg) is less than either of L_(md) or L_(ms).
 12. The Field Effect Transistor structure recited in claim 10 wherein: the source electrode is within opposing outer edges the Group III-V semiconductor region separated a length L_(ms); the drain electrode is within opposing outer edges the Group III-V semiconductor region separated a length L_(md); the first portion of the gate is within the pair of notches having a separation a length L_(mg); where L_(mg) is less than either of L_(md) or L_(ms).
 13. The Field Effect Transistor structure recited in claim 9 wherein the Group III-V semiconductor region comprises a mesa structure.
 14. The Field Effect Transistor structure recited in claim 11 wherein the Group III-V semiconductor region comprises a mesa structure.
 15. The Field Effect Transistor recited in claim 9 wherein the gate electrode is spaced from the source region and the drain region.
 16. The Field Effect Transistor recited in claim 9 wherein a carrier control portion of the first portion of the gate electrode controls the flow of carriers between the source electrode and the drain electrode through an active region closest to the source electrode and the drain electrode; wherein the notch is separated from the active region closest to the source electrode and the drain electrode by a portion of the Group III-V semiconductor region; and wherein the carrier control portion of the first portion of the gate electrode is in Schottky contact with only the upper surface of the Group III-V semiconductor region. 